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可编程通用逻辑门阵列芯片简称FPGA，与CPU，DSP并列为三大通用数字处理芯片，广泛应用于通信、航空航天、医疗、国防军工以及安防视频监控等领域。通过本书的学习，读者可以全面了解一颗FPGA芯片从设计、验证到流片的全部开发过程。本书共分10章，采取“总—分”的编排方式。第1章从架构的总体设计入题对FPGA进行介绍。第2~10章，分别对其中的各个重要模块逐一介绍，包括：时钟网络、电源/地线网络和漏电流、可编程逻辑单元、可编程I/O模块、DDR存储器接口、数字延时锁定环、连线连接盒、互连线段长度分布以及配置模块。本书适合从事集成电路设计的资深工程师、微电子专业高年级研究生以及从事微电子专业教学研究的教师和科研人员阅读。本书还可以作为高等院校教授集成电路设计的辅助资料。

第1 章 FPGA 架构总体设计 ········································································· 1
1.1 FPGA 芯片研制流程·········································································· 1
1.2 FPGA 架构设计流程·········································································· 7
1.3 FPGA 规模和资源划分 ····································································· 17
1.4 FPGA 中功能模块划分 ····································································· 20
本章参考文献 ······················································································ 26
第2 章 FPGA 中时钟网络 ·········································································· 30
2.1 简介 ···························································································· 30
2.2 FPGA CDN 建模 ············································································· 33
2.3 时钟网络设计方法 ·········································································· 43
2.4 时钟网络的灵活性 ·········································································· 48
2.5 路由级联 ······················································································ 51
2.6 仿真实验 ······················································································ 55
2.7 时钟网络热学建模 ·········································································· 61
2.8 仿真实验 ······················································································ 62
本章参考文献 ······················································································ 66
第3 章 FPGA 中电源/地线网络和漏电流 ······················································· 68
3.1 电源/地线网络 ··············································································· 68
3.2 IR-DROP 分析与优化 ········································································ 71
3.3 漏电流组成 ··················································································· 73
3.4 降低漏电流的方法 ·········································································· 74
3.5 基于VIA 分布的IR-DROP 分析 ··························································· 77
3.6 仿真实验 ······················································································ 81
3.7 不均匀测试点的IR-DROP 求解 ··························································· 87
3.8 FPGA 电源网络IR-DROP 分析 ···························································· 89
本章参考文献 ······················································································ 94
第4 章 FPGA 中可编程逻辑单元 ································································· 98
4.1 基于多路选择器的逻辑单元 ······························································ 98
4.2 基于四输入LUT 的可编程逻辑单元的设计 ·········································· 102
4.3 LUT 的模型与实现 ········································································ 103
4.4 LUT 的输入数目K 的确定 ······························································· 106
4.5 进位逻辑 ····················································································· 109
4.6 基于查找表结构的FPGA 的不足 ······················································· 115
4.7 AIC 结构逻辑簇 ············································································ 117
4.8 基于AIC 结构FPGA 的逻辑簇 ························································· 120
4.9 面向AIC 的映射工具及结构评估平台 ················································ 124
4.10 结构特征匹配的AIC 簇互连优化 ···················································· 125
4.11 仿真分析和比较 ·········································································· 131
本章参考文献 ····················································································· 133
第5 章 FPGA 中可编程I/O 模块 ································································· 136
5.1 可编程I/O 系统结构 ······································································ 136
5.2 IOE 中的可编程输入缓冲器设计 ······················································· 138
5.3 IOE 中的可编程输出缓冲器设计 ······················································· 144
5.4 可编程I/O 的后端版图设计······························································ 156
5.5 高可靠I/O 模块的后端版图与测试 ····················································· 166
5.6 可编程I/O 的供电策略 ··································································· 172
5.7 全芯片IO 的ESD 技术 ··································································· 173
本章参考文献 ····················································································· 179
第6 章 FPGA 中DDR 存储器接口 ······························································ 182
6.1 DDR SDRAM 芯片的工作原理 ·························································· 182
6.2 FPGA 芯片中DDR 存储器接口系统设计 ············································· 184
6.3 DDR 存储器接口控制器的设计和验证 ················································ 191
6.4 延时锁相技术 ··············································································· 194
6.5 延时锁定环电路的分析与对比 ·························································· 196
6.6 数字延时锁定环电路的性能分析与优化 ·············································· 201
6.7 延时锁定环线性模型与稳定性分析 ···················································· 205
本章参考文献 ····················································································· 209
第7 章 FPGA 中数字延时锁定环 ································································ 213
7.1 实现相移的全数字延迟锁定环 ·························································· 213
7.2 数字控制延时链 ············································································ 215
7.3 时间数字转换器 ············································································ 220
7.4 双向移位计数器 ············································································ 221
7.5 鉴相器与锁定逻辑 ········································································· 222
7.6 延迟锁定环的版图设计 ··································································· 224
7.7 延迟锁定环环路的仿真 ··································································· 224
7.8 芯片的物理实现与测试平台 ····························································· 225
7.9 DDR 接口的数据通路的测试验证 ······················································ 227
7.10 数字延时锁定环的测试 ································································· 229
7.11 数字占空比矫正电路的测试 ···························································· 232
本章参考文献 ····················································································· 234
第8 章 FPGA 中连线连接盒 ······································································ 236
8.1 引言 ··························································································· 236
8.2 问题分析 ····················································································· 237
8.3 利用模拟退火算法优化CB 拓扑结构 ·················································· 241
8.4 实验及结果分析 ············································································ 246
8.5 连线开关盒的电路结构设计方法 ······················································· 251
本章参考文献 ····················································································· 259
第9 章 FPGA 中互连线段长度分布 ····························································· 261
9.1 所提优化方法的基本思路 ································································ 261
9.2 以面积延时积最小为目标的优化 ······················································· 265
9.3 针对所提优化方法的讨论 ································································ 268
9.4 设计实验 ····················································································· 269
9.5 FPGA 芯片的设计实现 ···································································· 270
9.6 芯片的测试准备 ············································································ 272
本章参考文献 ····················································································· 275
第10 章 FPGA 中的配置模块 ···································································· 277
10.1 配置系统的基本组成及特点 ···························································· 277
10.2 配置系统的功能需求 ···································································· 279
10.3 配置系统的硬件结构分析 ······························································ 281
10.4 配置码流协议的结构及其对配置系统的影响 ······································· 286
10.5 配置系统总体框架 ······································································· 292
10.6 配置码流协议的设计 ···································································· 297
10.7 配置系统的电路设计与实现 ···························································· 300
10.8 配置系统采用的验证工具与方法 ······················································ 305
10.9 配置系统的验证方案与功能点的抽取 ················································ 310
10.10 配置系统功能验证平台的设计 ······················································· 312
10.11 配置系统验证结果 ······································································ 319
本章参考文献 ····················································································· 324

前 言
2006 年9 月在北航攻读集成电路设计专业硕士开始，至2015 年4 月从中科院电子所微电子与固体电子学博士后出站，恍惚间，从事集成电路相关的设计和研究工作已经十年了。这十年也正是中国半导体行业，更确切地讲，是集成电路设计行业飞速发展的十年。
记得刚读硕士时，接触到人生第一块FPGA 开发板，用的是Xilinx 公司的Spartan3系列。从点亮第一个跑马灯例子的兴奋，到一步一步跟着JPEG 解码设计小组完成逐个模块的设计，验证和调试。阻塞赋值与非阻塞赋值，竞争与冒险，建立和保持时间等等……，看着一个个小知识点被融入到自己的设计中，成就感油然而生。就这样，调试正确时的兴奋和无法找到Bug 时的煎熬，交织在每一个奋力调试的夜晚。毕业后，进入了一家日资的集成电路设计公司，开始了全职从事专用芯片的设计和验证工作。期间，我意识到代码设计仅仅占到整个开发过程的一小部分，系统规划、设计流程和文档规范性对开发工作而言才是重中之重。在日资公司的这一年，我完成了数个模块级的设计和一个全芯片系统级验证工作，积累了丰富的实战经验，也是我职业发展的起点。
此后，在中科院电子所攻读博士学位和博士后的六年，一直从事FPGA 芯片的设计与研制工作，并有幸加入国内从事FPGA 芯片设计最顶尖的团队——可编程芯片与系统研究室。从芯核组、IO 组再到产品组，我对于如何设计一颗好的芯片的理解也在逐步加深。
所谓不忘初心，方得始终。虽然现在我已经离开了中科院系统，进入了大学任教。在成书过程中，以前可编程芯片与系统研究室的各位同事都给了我很多帮助，其中，孙嘉斌、李威、王一、黄志红、张甲、陈柱佳、舒毅的设计和仿真实验是构成本书的基础，非常感谢他们无私的帮助。感谢我的导师杨海钢研究员，他一直以努力工作的实际行动给我以最有力的鼓励和鞭策，使我不能懈怠。
目前，市面上关于FPGA的书都是基于FPGA的应用设计方面的介绍，而关于FPGA芯片设计的书籍尚未出版，本书的出版恰好填补了这项空白。
本书基于集成电路的全定制与自动化混合设计流程，系统的剖析了一颗FPGA 芯片从架构规划、模块设计、系统验证、流片到封装与测试的全过程，并对其中的核心模块详述了电路级设计与实现方法。全书共分10 章，其中第1 章阐述FPGA 架构的总体设计；从第2 章开始分类介绍各种核心模块的设计、仿真和验证过程等。在成书的过程中，感谢电子工业出版社和本书的责任编辑大力支持，本书才得以
与广大读者见面。此书错误疏漏之处恳请广大读者批评指正。同时也欢迎大家就FPGA 芯片的开发
与设计相关技术与作者交流。
余乐
2016 年12月
于北京

电子电路

申请人于2009年3月至2012年8月在中科院电子所可编程芯片与系统研究室攻读博士学位，从事下一代SOC FPGA的关键集成技术研究。博士课题来源于中科院/国家外专局的创新团队国际合作伙伴计划"片上可编程系统前沿技术研究”。博士毕业获微电子与固体电子学博士学位。同年，以申请人博士论文为基础，帮助实验室申请了国家自然科学基金面上项目"基于TSV互连的三维FPGA架构及关键技术研究”。__eol__2012年博士毕业后，选择留所继续从事博士后研究工作，并作为国自基金项目的实际负责人，管理项目的整体推进，指导学生完成了2篇论文的投稿。博士后期间，参与了两款FPGA芯片的研制工作，分别是0.13um 百万门级FPGA（中科院重点方向性项目）和40nm FPGA-ip核（国家重大专项）。2015年博士后出站，出站报告"FPGA时钟分布网络研究”从延时、面积、功耗、灵活性以及热性能等多方面，对FPGA的关键架构技术进行了研究。__eol__

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FPGA芯片架构设计与实现